MC9S12DJ128B |
RFQ for MC9S12DJ128B Required Field |
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| Technical/Catalog Information | MC9S12DJ128BCFU |
| Vendor | Freescale Semiconductor |
| Category | Integrated Circuits (ICs) |
| Program Memory Size | 128KB (128K x 8) |
| RAM Size | 8K x 8 |
| Number of I /O | 59 |
| Package / Case | 80-QFP |
| Speed | 25MHz |
| Controller Series | HCS12 |
| Oscillator Type | Internal |
| Packaging | Tray |
| Program Memory Type | FLASH |
| EEPROM Size | 2K x 8 |
| Core Processor | HCS12 |
| Data Converters | A/D 16x10b |
| Core Size | 16-Bit |
| Operating Temperature | -40°C ~ 85°C |
| Connectivity | CAN, I²C, SCI, SPI |
| Peripherals | PWM, WDT |
| Voltage - Supply (Vcc/Vdd) | 2.35 V ~ 2.75 V |
| Drawing Number | 375; 841B-02; FU; 80 |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | MC9S12DJ128BCFU MC9S12DJ128BCFU |
| Product | Manufacturers | Pack | D/C |
| MC9S12DJ128B | - | QFP80 | - |
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.
Features |
| • HCS12 Core 16-bit HCS12 CPUi. Upward compatible with M68HC11 instruction setii. Interrupt stacking and programmer's model identical to M68HC11iii.20-bit ALUiv. Instruction queuev. Enhanced indexed addressing MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) INT (Interrupt control) BKP (Breakpoints) BDM (Background Debug Mode)• CRG (Clock and Reset Generator) Choice of low current Colpitts oscillator or standard Pierce Oscillator PLL COP watchdog real time interrupt clock monitor• 8-bit and 4-bit ports with interrupt functionality Digital filtering Programmable rising or falling edge trigger• Memory 128K Flash EEPROM 2K byte EEPROM 8K byte RAM• Two 8-channel Analog-to-Digital Converters 10-bit resolution External conversion trigger capability• Three 1M bit per second, CAN 2.0 A, B software compatible modules Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function Loop-back for self test operation• Enhanced Capture Timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators• 8 PWM channels Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs• Serial interfaces Two asynchronous Serial Communications Interfaces (SCI) Two Synchronou |
| Num | Rating | Symbol | Min | Max | Unit |
| 1 2 3 4 5 6 7 8 9 10 11 12 13 |
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 2 PLL Supply Voltage 2 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 Instantaneous Maximum Current Single pin limit for TEST 5 Storage Temperature Range |
VDD5 VDD VDDPLL DVDDX DVSSX VIN VRH, VRL VILV VTEST ID IDL IDT Tstg |
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 65 |
6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155 |
V V V V V V V V V mA mA mA °C |
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute ma
